1. Field of the Invention
The invention relates to an integrated, programmable logic arrangement of the type which includes an AND matrix and an OR matrix, each matrix being provided with individual gates, and each matrix is programmed by the provision or absence of a switching transistor at the intersections of control lines and selector lines, the control lines of the AND matrix constituting inputs, the selector lines of the OR matrix constituting outputs, and the selector lines of the AND matrix connected to the control lines of the OR matrix.
2. Description of the Prior Art
Integrated, programmable logic arrangements of the type generally described above are well known in the art and are referred to as programmable logic arrays (PLA). These arrays comprise two series-connected, programmable gate collectives, an AND matrix and an OR matrix. Such arrangements are described, for example, in the publication by W. Carr & J. Mize: MOS/LSI Design and Application, McGraw-Hill Book Co., New York, 1972, pp. 229-258. A known logic arrangement of this type is represented in the first figure of the drawings of the instant case, in which an AND matrix 01 comprises individual gates, each gate in turn comprising parallel-connected switching transistors. In each case, one gate terminal of a switching transistor is connected to a control line. For example, in the AND matrix 01 the switching transistor 014 and 017 form a gate. The switching transistor 014 is connected to the control line 0141 which is itself connected to an input E.sub.1. The switching transistor 017 is connected to the control line 0171 which is connected, via an inverter 019, to an input E.sub.2. On the one hand, the switching transistor 014 and 017 are connected, via the line 0131 to ground, and, on the other hand, the switching transistor 014 and 017 are connected to a gate line 0111. The supply voltage U.sub.DD is applied to the gate line 0111 by way of a load transistor 011.
Individual gates are arranged in a corresponding fashion in the OR matrix 02.
Integrated, programmable logic arrangements of this type have the disadvantage that the gates of the matrices 01 and 02 conduct rest currents in one of the two possible switching states, in which case an increased power loss and an adulteration of the logic level occurs. Also, since the load transistors 011, 012, 021 and 022 cannot be made with a sufficient low-ohmic resistance, charging processes across these load transistors are relatively slow and therefore limit the operative speed of the logic arrangement.